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JPEG2000 Coder RB5C634A

Data Sheet

Ver.1.1.6

The RB5C634A is a one-chip coder equipped with image compression function of generating JPEG2000-compliant codes and decompression function of decoding images from the JPEG2000-compliant codes. Because of its superior capability of creating the whole codestream including a main header, the RB5C634A is able to provide powerful encoding and decoding functionality that is attained simply by setting up parameters in the internal registers. Using this coder, an image of up to 1024 x 1024 pixels can be processed within one tile, which presents you with the ideal solution for reducing the degradation in image quality to a large extent, even at the high compression level.

In addition, so-called rate control is supported; thus promising the flexible capability of controlling compressed codes to any size.

With all these capabilities, the RB5C634A enables accurate and thorough control over the images, on a frame-basis, to be stored without fail in predetermined storage devices. The RB5C634A will be one of the best solutions to users seeking out precise image control, both in number and quality.

I/O image data

Precision:	8 bits/color/pixel when using IR9-7; 8, 10, 12 bits/color/pixel when using R5-3.
Sampling format:	1) YCbCr 4:2:2 (H2V1) 2) YCbCr 4:0:0 (Grayscale)
Image size:	Processes images of any size up to 1024 x 1024 pixels, in one-tile.

Wavelet filter
Selectable between R5-3 filter and IR9-7 filter

Codestream

•	Rate control function that enables generation of a specific amount of codes
•	Code recompression function (Code input -> Code compression -> Code output)

The Ricoh-proprietary algorithms allows automatic truncation so that the optimum image quality can be obtained and generation of codes of the specified amount.

Header processing
Automatically generates a main header, a tile part header, and a packet header during compression, and interprets them during decompression, internally.

Decompression of reduced images
Using the same code, a reduced image can be decompressed to the size of 1/1, 1/4, 1/16, 1/64, 1/128, and 1/256 of the original image.

Processing speed

•	With truncation: maximum of about 31M pixels/sec
	For an image of 720 x 480 pixels (4:2:2), 90 frames can be compressed or decompressed per second. (In such case, compression rate should be set to about 1/30.)
•	Without truncation: maximum of about 27M pixels/sec
	(Lossless when using R5-3 filter.)

Interface

Image data interface is selectable from the following two:

•	VSYNC Image Interface based on VSYNC, HSYNC, and FIELD input
	Use this mode when connecting with a general-purpose video coder or encoder
•	Image Frame Interface that transfers image data on a frame basis using handshake method

Code data interface is selectable from the following two:

•	16-bit Code Interface in the clock-based handshake method
•	Access via PCI bus (target access)

Local data interface

8-bit wide local bus is used to enable data read/write from/to the internal registers.
However, if the PCI bus is selected as the code data interface, access is enabled through the PCI.

SDRAM interface

32-bit wide SDRAM interface. SDRAM is used as storage of image data and as a work field during processing. Connect SDRAM of 64M bits or more.

Miscellaneous

•	Clock for Image data interface:
	VSYNC Image mode:	Max. 33 MHz
	Image Frame mode:	Max. 45 MHz
•	Clock for internal operations and SDRAM interfaces:	Max. 90 MHz, Min. 40 MHz
	(The minimum value is specified according to the lock range of the incorporated PLL for SDRAM clock phase focusing)
•	Clock for the PCI/local bus and Code Interface:	Max. 33 MHz
•	I/O voltage: 3.3 V, Internal power supply voltage: 1.8 V
•	PLL incorporated for SDRAM clock frequency synthesis
•	Package: 272-pin BGA (size= 27 mm x 27 mm, pitch= 1.27 mm)
	272-pin BGA (PDF 86KB)